The ‘Registers’ for ALU and Control Unit
The control unit operates the IAS by fetching instructions from memory and executing them one at a time.Both the control unit and the ALU contain storage locations in CPU, called registers, defined as follows:
Structure of IAS
ALU Registers
Memory Buffer Register (MBR): contains a 40-bit word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit.Accumulator (AC) and Multiplier Quotient (MQ): are employed to hold temporarily operands and results of ALU operations.
For example, the result of multiplying two 40-bit numbers is an 80-bit number; the most significant 40 bits are stored in the AC and the least significant in the MQ.
Program Control Unit Registers
Memory Address Register (MAR): is a 12-bit register that specifies the address in memory of the word to be written from or read into the MBR.
Instruction Register (IR): contains the 8-bit opcode instruction being executed by the ‘control circuits’ e.g. add, multiply.
Instruction Buffer Register (IBR): is employed to hold temporarily the right-hand instruction of 20-bit from a word in Memory. While the left-hand instruction goes to IR and MAR (20-bit).
Program Counter (PC): contains the address of the next instruction pair to be fetched from memory.
What is an ‘Instruction Cycle’?
Each ‘instruction cycle’ consists of two sub-cycles,
1) Fetch cycle 2) Execute cycle
Instruction cycle is the process by which a computer retrieves a program instruction from its memory called fetch cycle.
Then it determines what actions the instruction dictates, and carries out those actions called execute cycle.
Steps of ‘Instruction Cycle’: Fetch-Decode-Execute
To execute a program, the program code is copied from secondary storage into the main memory.
In a program, each machine code instruction takes up a slot in the main memory.
These slots (or memory locations) each have a unique memory address.
The CPU's program counter is set to the memory location where the first instruction in the program has been stored and execution begins.
PC register tells the CPU the order of instructions, a program is running.
When a program is being executed, the CPU repeats this cycle again.
The Operation of the IAS (Fetch Cycle)
The IAS operates by repetitively performing an instruction cycle.
Each ‘instruction cycle’ consists of two sub-cycles, fetch cycle and execute cycle.
During the fetch cycle, the opcode of the next instruction is loaded into the IR and the address portion is loaded into the MAR.
This instruction may be taken from the IBR, or it can be obtained from memory by loading a word into the MBR, and then down to the IBR, IR, and MAR.
The Operation of the IAS (Execute Cycle)
Once the opcode is in the IR, the execute cycle is performed.For Example The opcode: 00000101 is interpreted by the ‘control circuit’ as ADD M(X), and it Adds M(X) to AC and puts the result in AC.
