Bus Interconnection
- A bus is a shared transmission medium.
- A Bus is a communication pathway connecting two or more devices.
- A bus consists of multiple communication pathways, or lines, often grouped. A System Bus connects major computer components.
A number of line/channel in one bus, each capable of carrying one bit.
Over time, a sequence of binary digits can be transmitted over a single line.
Taken together, several lines of a bus can be used to transmit binary data simultaneously (in parallel).
e.g. 32-bit data bus is 32 separate single bit channels.
For example, an 8-bit unit of data can be transmitted over eight bus lines.
Types of Buses
A system bus consists typically, of from about fifty to hundreds of separate lines.
Each line is assigned a particular meaning or function.
The bus lines can be classified into three groups:
1) Address lines (bus) 2) Data lines (bus) 3) Control lines (bus)
In addition, there may be power distribution lines to the attached module.
1. Data Bus
- The data lines provide a path for moving data among system modules.
- These lines, collectively, are called the data bus.
- The data bus may consist of 32, 64, 128 or even more separate lines.
- Each line can carry only one bit at a time, the number of lines determine how many bits can be transferred at a time.
- The number of these data lines are called the width of the data bus.
- The width of the data bus determines the overall system performance.
- For example, if the data bus is 32 bits wide and each instruction is 64 bits long, then the processor must access the memory module twice during each instruction cycle. (e.g. two fetch operations in each line)
2. Address Bus
- The address lines are used to designate the source or destination of the data on the data bus.
- If the processor wishes to read a word (8, 16 or 32 bits) of data from memory, it puts the address of the desired word on the address lines.
- The width of the address bus determines the maximum ‘memory capacity’ of the system. (i.e. more bits mean more memory locations)
- E.g. 8080 has 16 bit address bus giving 2^16 = 64k address space.
- Furthermore, the address lines are also used to address I/O ports.
- The higher-order bits are used to select a particular module on the bus, and the lower-order bits select a memory location or I/O port.
3. Control Bus
- The control lines are used to control the access to and the use of the data and address lines.
- Because data and address lines are shared by all components, there must be a means of controlling their use.
- Control signals transmit both command and timing information among system modules. (Control Unit)
- Timing signals indicate the validity of data and address information.
- Command signals specify operations to be performed.
- Typical control line signals are given in the next slide.
Control Line Signals
Limitations of Bus Design
A bus is a shared transmission medium.
Multiple devices connect to the bus, and a signal transmitted by any one device is available for reception by all other devices attached to the bus.
If two devices transmit during the same time period, their signals will overlap and will become garbled (Make false by subtract or addition).
Thus, only one device at a time can successfully transmit.
We need to set up rules so that only one device can take control of the bus at a time.
Bus Operation Explained
If one module wishes to send data to another, it must do two things:
Obtain the use of the bus, using ‘bus request’ control signal.
Transfer data via the bus, using memory write or I/O write signal.
If one module wishes to request data from another module, it must:
Obtain the use of the bus, using ‘bus request’ control signal.
Transfer a request to the other module over the appropriate control and address lines, using memory read or I/O read control signal.
It must then wait for the second module to send the data.
Single-Bus Problems
If a great number of devices are connected a single bus, performance will suffer. There are two main causes:
In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay.
Delay in co-ordination of bus use can adversely affect performance.
The bus may become a bottleneck as the aggregate data transfer demand approaches the capacity of the bus.
This problem can be countered to some extent by increasing the data rate that the bus can carry and by using wider buses.
Solution: Instead of a single –bus, use multiple buses in a hierarchy.
Traditional Bus Architecture
