What is an ‘Instruction Set Architecture (ISA)’?
- The ISA serves as the interface between software and hardware.
- The ‘instruction set’ provides commands to the processor, to tell it what it needs to do.
- An ISA defines everything a machine language programmer needs to know in order to program a computer.
- The instruction set consists of addressing modes, instructions, native data types, registers, memory architecture, interrupt, and external I/O.
Approaches to Processor Design
The two approaches to processor design are:
1) CISC 2) RISC
Complex instruction set computing (CISC):
is a processor design, where single instructions can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) or are capable of multi-step operations or addressing modes within single instructions.
Reduced instruction set computing (RISC):
has a set of attributes that allows it to have lower cycles per instruction (CPI) than a (CISC). RISC concept is that of a computer that has a small set of simple and general instructions. RISC processors only use simple instructions that can be executed within one clock cycle.
Multiplication Example (CISC)
Processor performance is measured by the rate at which instructions are executed, expressed as Millions of Instructions Per Second (MIPS).
For example, consider this high-level language statement:
A = A * B; Assume all quantities in main memory
With a traditional Complex Instruction Set Computer (CISC), this instruction can be compiled into one processor instruction:
MULT mem(A), mem(B)
If the CISC machine is rated at 1MIPS. This is done in one clock cycle.
Multiplication Example (RISC)
On a RISC, the Multiply command described previously can be divided into three separate commands (LOAD, MUL, STORE).
On a typical Reduced Instruction Machine (RISC), the compilation would take four machine instructions:
LOAD R1, mem(A)
LOAD R2, mem(B)
MUL R1, R2
STORE mem(A), R1
RISC machine would be rated at 4MIPS. And takes four clock cycles.
Both CISC & RISC would do the same amount of high-level language work in the same amount of time. (RISC takes more line of code).
1. CISC Architecture
- The earliest Intel processors for the IBM Personal Computer were based on what is called a Complex Instruction Set (CISC) approach.
- The Intel instruction set includes powerful ways to address data, and instructions that are relatively high-level complex operations.
- The CISC philosophy was that high-level language compilers would have less work to do if individual machine-language-instructions were powerful.
- A major disadvantage to the CISC approach is that ‘complex instructions’ require a relatively ‘long time’ for the processor to decode and execute. (because they have several low-level operations)
- An ‘interpreter program’ inside the CPU written in a language called microcode decodes and executes each machine instruction.
- Each complex instruction can take different machine cycles based on its complexity. (hence pipeline approach is not possible in CISC).
- Once Intel committed to a complex instruction set, it was necessary for all subsequent Intel processors to be compatible with the first one.
- Software written for the original IBM Personal Computer can still run on today’s latest Pentium.
- The only advantage is that the user code in CISC is ‘small source code’.
CISC Advantages (Adv) & Disadvantages (Dis)
Adv: Source code programs are short; fewer instructions; this saves memory space.
Dis: Memory is now much inexpensive, this is not an advantage.
Dis: The number of bits of memory occupied by a CISC program (in machine language) may not be noticeably small (heavy programs).
Dis: Using complex and fewer instructions, code size cannot be reduced/optimized by the programmer (inflexible).
Dis: The individual instructions are complex, and they take a long time to decode and execute.
Adv: Fewer instructions in a code means fewer instruction bytes to be fetched. (reducing fetch operations)
Dis: CISC uses memory references for operands, which is much slower.
Dis: There are more instructions on a CISC, longer opcodes are required, producing longer instructions. (instructions lengths vary)
Dis: Each instruction takes different clock cycles to execute, so in CISC, the pipeline is not possible. (to execute multiple instructions in parallel)
Adv: A complex High-Level Language (HLL) operation will execute more quickly in a single machine instruction (cycle).
Dis: The entire ‘control unit’ must be made more complex, this increases the execution time of the simple instruction. (microcode)
2. RISC Architecture
- A completely different approach to microprocessor design is called Reduced Instruction Set (RISC).
- A RISC machine language consists of a relatively small number of short, simple instructions that can be executed very quickly (in a single clock cycle).
- Rather than using a ‘microcode interpreter’ to decode and execute machine instructions, a RISC processor directly decodes and executes instructions using hardware.
- Intel recognized many advantages to the RISC approach and found a way to use RISC-like features (such as pipelining and superscalar) in its Pentium processors.
RISC Architecture (Key Elements)
RISC architecture key elements are these:
- A large number of general-purpose registers (GPRs), and/or the use of compiler technology to optimize register usage.
- A limited and simple instruction set.
- An emphasis on optimizing the instruction pipeline.
RISC Characteristics
- RISC characteristics are:
- One instruction per cycle
- Register-to-register operations
- Simple addressing modes
- Simple instruction formats
E.g. in CISC: Add R1,R2,R3 => R1 = R1 + R2+R3 is a single instruction.
Whereas in RISC: Add R2, R3 and Add R1, R2 are two separate lines.
One Instruction Per Cycle (RISC)
- In RISC there is one machine instruction per machine cycle.
- A machine cycle is defined to be the time (cycles) it takes to fetch, store or perform an arithmetic operation. (usually done in one cycle)
- With simple, one cycle instruction, there is little or no need for microcode; the machine instructions can be hardwired.
- Such instructions should execute faster because it is not necessary to fetch a microprogram code during instruction execution as in CISC.
RISC Advantages
- The instructions are simple/primitive, and they execute fast.
- RISC uses registers to access operands, which are much faster to read.
- Instruction length is fixed, especially the opcode so opcode decoding and register operand accessing can occur simultaneously.
- The source code is long, but it is flexible enough to be optimized.
- Because each instruction takes one clock cycle, instruction pipelining is possible. This improves processor operating speed.
- RISC processors are more responsive to interrupts because interrupts are checked between each small instruction/every machine cycle.
CISC vs RISC (Comparison)
